1. Field of the Invention
This invention relates to a cell structure digital multiplier of semi-systolic construction.
2. Description of the Prior Art
Multipliers are described in the article by J. R. Jump and S. R. Ahuja entitled "Effective Pipelining of Digital Systems" in the magazine entitled IEEE Transactions on Computers Vol. C-27, No. 9, September 1978, pages 855-865 and in particular at FIG. 7(b). A disadvantage of the multiplier described in this article is that in particular in case of multiplicands having large word links, the two input lines which each supply a multiplier bit to all of the cells of a row must be provided with driver circuits which have transit times together with a transit times of the components of the second input lines which are located between the driver circuits and the cells under consideration substantially delay the supply of the multiplier bits. This results in a substantial increase in the stage transit time which passes between the emission of the sums and carry signals from the outputs of the shift register stages of a row and the emission of corresponding signals at the outputs of the shift register stages of the next row.